1. Field of the Invention
The present invention relates to high performance computers; and, in particular, relates to high performance computers providing a large virtual memory space.
2. Description of the Related Art
A virtual memory system provides a computer programmer a large conceptual address space which is typically implemented in a much smaller physical address space for practical reasons. The physical addresses in the physical address space are used to access physical memory locations in which data or instructions are actually stored. The functions and the benefits of a virtual memory system are well-known.
Modern memory systems are almost always paged. Thus, in a virtual memory system supporting paging, to translate a virtual memory address into a physical memory address, a page table is used to map a portion of the virtual memory address into a corresponding physical memory page address, which is then used to derive the physical memory address.
In implementing such a virtual memory system, numerous approaches have been used to minimize the delay caused by looking up the page table. One such approach uses a translation look-aside buffer (TLB). A TLB, which is often content addressable using the virtual memory address, caches a number of the page table entries in current active use. In recent years, some designs, such as the Mips R2000, have implemented two levels of TLBs, taking advantage that a smaller but faster first level TLB can be implemented economically to cache page table entries in the larger but slower second level TLB.